#!/bin/sh

#-----------------------------------------------------------------------------
# Script to synthesize and implement the RapidIO End Point Solution
#-----------------------------------------------------------------------------

# Clean up the results directory
rm -rf results
mkdir results

# Copy unisim_comp.v file to results directory
cp $XILINX/verilog/src/iSE/unisim_comp.v ./results/

# Generate CS components
cd ../example_design/chipscope
coregen -b phy_ila.xco
coregen -b rio_ila.xco
coregen -b srio_vio.xco
coregen -b srio_icon.xco
cd ../../implement

# Synthesize the Verilog Wrapper Files
echo 'Synthesizing Verilog RapidIO End Point design with XST'
xst -ifn xst.scr
cp srio_v5_4_top.ngc results/

#  Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
cp ../example_design/srio_v5_4_top.ucf results/

cd results

echo 'Running ngdbuild'
ngdbuild -sd ../../ -sd ../../netlists/ -sd ../../example_design/chipscope/  -uc srio_v5_4_top.ucf srio_v5_4_top

echo 'Running map'
map -ol high -timing -pr b srio_v5_4_top -o mapped.ncd

echo 'Running par'
par -ol high -w mapped.ncd routed mapped.pcf

echo 'Running trce'
trce -e 10 routed -o routed mapped.pcf

echo 'Running design through bitgen'
bitgen -w routed

echo 'Running netgen to create gate level Verilog model'
netgen -ofmt verilog -sim -tm srio_v5_4_top -w routed.ncd routed.v

cd ..
